Rockwell Automation 1746-HSCE,D17466.5 High-Speed Counter Module - Manual (Page 157)

Publication 1746-UM006B-EN-P - August 2005
M0 and M1 Files B-3
If you need to show the state of the M0 or M1 addressed bit, you can
transfer the state to an internal processor bit. This is illustrated below,
where an internal processor bit is used to indicate the true/false state
of a rung.
M0/M1 Monitoring Option Enabled
The SLC 5/03, SLC 5/04, and SLC 5/05 processors allow you to
monitor the actual state of each addressed M0/M1 address (or data
table). The highlighting appears normal when compared to the other
processor data files. The processor’s performance will be degraded to
the degree of M0/M1 referenced screen data. For example, if your
screen has only one M0/M1 element, degradation will be minimal. If
your screen has 69 M0/M1 elements, degradation will be significant.
IMPORTANT
This option is not supported by the SLC 5/02
processor.
This rung will not show its true rung state because the EQU instruction is always shown
as true and the M0 instruction is always shown as false.
OTE instruction B3/2 has been added to the rung. This instruction shows the true or
false state of the rung.
] [
B3
0
] [
B3
1
( )
M0:3.0
1
( )
M0:3.0
1
] [
B3
0
] [
B3
1
( )
B3
2
EQU
EQUAL
Source A
N7:12
Source B N7:3
EQU
EQUAL
Source A
N7:12
Source B N7:3