Kontron CG2100 Carrier Grade Server - Manual (Page 30)

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The integrated memory controller in the Intel ® Xeon ® Processor 5600 Series alternates
between both channels for read transactions. Write transactions are issued to both
channels under normal circumstances.
When the system is in the Channel Mirroring mode, channel C and channel F of socket 1
and socket 2 respectively are not used. Thus, the DIMMs populated on these channels
are disabled and do not contribute to the available physical memory. For example, if
the system is operating in Channel Mirroring mode and the total size of the DDR3 DIMMs
is 1.5 GB (3 x 512 MB DIMMs), then the active memory is only 1 GB.
Because the available system memory is divided into a primary image and a copy of the
image, the system memory is reduced by at least one-half. For example, if the system
is operating in the Channel Mirroring mode and the total capacity of the DDR3 DIMMs is
1 GB, then the effective size of the memory is 512 MB because half of the DDR3 DIMMs
are the secondary images.
For channel mirroring to work, DDR3 DIMMs in the same slots on adjacent channels must
be identical in terms of technology, number of ranks, and size. DIMMs within the
channel do not need matching parameters.
The BIOS setup provides an option to enable mirroring if the current DIMM population
is valid for channel mirroring. When memory mirroring is enabled, the BIOS attempts to
configure the memory system, if the BIOS finds that the DIMM population is not
suitable for mirroring, it falls back to the default Channel Independent mode with
maximum memory interleaving.
Minimum DDR3 DIMM Population for Channel Mirroring
Memory mirroring has the following minimum requirements:
• Channel configuration: Mirroring requires the first two adjacent channels to be
active.
• Socket configuration: Mirroring requires that both socket 1 and socket 2 DIMM
population meets the requirements for mirroring mode. The platform BIOS configures
the system in mirroring mode only if both nodes qualify. The only exception to this
rule is when all socket 2 DIMM slots are empty.
Because of these requirements, the minimal DIMM population is {A1, B1}. In this
configuration, processor cores on socket 2 suffer memory latency from the remote
memory on socket 1. An optimal DIMM population for channel mirroring in a DP server
platform is {A1, B1, D1, E1}. {A1, B1} must be identical and {D1, E1} must be
identical. However, DIMMs do not need to be identical across sockets.
In this configuration, DIMMs {A1, B1} and {D1, E1} operate as (primary copy, secondary
copy) pairs independent from each other. Therefore, the optimal number of DDR3 DIMMs
for channel mirroring is a multiple of four, arranged as mentioned above. The BIOS
disables all non-identical DDR3 DIMMs or pairs of DDR3 DIMMs across the channels to
achieve symmetry and balance between the channels.
Mirroring DIMM Population Rules Variance Across Nodes
Memory mirroring in Intel ® Xeon ® Processor 5600 Series-based platforms is channel
mirroring. Mirroring is not done across sockets, so each socket may have a different
memory configuration. Channel mirroring in socket 1 and socket 2 is mutually
independent. As a result, if channel A and channel B DIMMs are populated identically
and channel D and channel E DIMMs are identically populated, then mirroring is
possible even if the DIMMs in each socket are not identical with the DIMMs in the
other socket, i.e., for channel A and channel D.
For example, if the system is populated with six DIMMS {A1, B1, A2, B2, D1, E1},
channel mirroring is possible. Both socket populations shown in the following table
are valid.
Table 4. Mirroring DIMM Population Rules Variance across Nodes