Document Outline

• Low Latency Ethernet 10G MAC User Guide
• Contents
• 1. About LL Ethernet 10G MAC
  • Features
  • Release Information
  • Device Family Support
    • Definition: Device Support Level
  • Performance and Resource Utilization
    • Resource Utilization
    • TX and RX Latency
• 2. Getting Started with LL Ethernet 10G MAC
  • Introduction to Altera IP Cores
  • Installing and Licensing IP Cores
  • Specifying IP Core Parameters and Options
  • Parameterizing the IP Core
  • Parameter Settings
  • Generated Files
  • Simulating Altera IP Cores in other EDA Tools
  • Upgrading Outdated IP Cores
  • Migrating IP Cores to a Different Device
  • Design Considerations
    • Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC
      • Migration—32-bit Datapath on Avalon-ST Interface
      • Migration—Maintains 64-bit on Avalon-ST Interface
    • Timing Constraints
      • Pseudo-Static CSR Fields
      • Clock Crosser
      • Dual Clock FIFO
• 3. Functional Description of LL Ethernet 10G MAC
  • Architecture
  • Interfaces
  • Frame Types
  • TX Datapath
    • Padding Bytes Insertion
    • Address Insertion
    • CRC-32 Insertion
    • XGMII Encapsulation
    • Inter-Packet Gap Generation and Insertion
    • XGMII Transmission
    • Unidirectional Feature
    • TX Timing Diagrams
  • RX Datapath
    • XGMII Decapsulation
    • CRC Checking
    • Address Checking
    • Frame Type Checking
    • Length Checking
      • Frame Length
      • Payload Length
    • CRC and Padding Bytes Removal
    • Overflow Handling
    • RX Timing Diagrams
  • Flow Control
    • IEEE 802.3 Flow Control
      • Pause Frame Reception
      • Pause Frame Transmission
    • Priority-Based Flow Control
      • PFC Frame Reception
      • PFC Frame Transmission
  • Reset Requirements
  • Supported PHYs
    • 10GBASE-R Register Mode
  • XGMII Error Handling (Link Fault)
  • IEEE 1588v2
    • Architecture
    • Transmit Datapath
    • Receive Datapath
    • Frame Format
      • PTP Packet in IEEE 802.3
      • PTP Packet over UDP/IPv4
      • PTP Packet over UDP/IPv6
• 4. Configuration Registers for LL Ethernet 10G MAC
  • Register Map
    • Mapping 10-Gbps Ethernet MAC Registers to LL Ethernet 10G MAC Registers
  • Register Access
  • Primary MAC Address
  • MAC Reset Control Register
  • TX_Configuration and Status Registers
  • Flow Control Registers
  • Unidirectional Control Registers
  • RX Configuration and Status Registers
  • TX Timestamp Registers
    • Calculating TX Timing Adjustments
  • RX Timestamp Registers
    • Calculating RX Timing Adjustments
  • ECC Registers
  • Statistics Registers
• 5. Interface Signals for LL Ethernet 10G MAC
  • Clock and Reset Signals
  • Speed Selection Signal
  • Error Correction Signals
  • Unidirectional Signals
  • Avalon-MM Programming Signals
  • Avalon-ST Data Interfaces
    • Avalon-ST TX Data Interface Signals
    • Avalon-ST RX Data Interface Signals
  • Avalon-ST Flow Control Signals
  • Avalon-ST Status Interface
    • Avalon-ST TX Status Signals
    • Avalon-ST RX Status Signals
  • PHY-side Interfaces
    • XGMII TX Signals
    • XGMII RX Signals
    • GMII TX Signals
    • GMII RX Signals
    • MII TX Signals
    • MII RX Signals
  • 1588v2 Interfaces
    • IEEE 1588v2 Egress Transmit Signals
    • IEEE 1588v2 Ingress Receive Signals
• A. Additional Information
  • Low Latency Ethernet 10G MAC User Guide Document Revision History