Fluke Biomedical 956A-201-M2 - Manual (Page 48)

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3.14 FUNCTIONAL DESCRIPTION UNIVERSAL DIGITAL
RATEMETER (UDR), MODEL 956A-201
The Model 956A-201 UDR is composed of five (5) circuit board assemblies mounted within the unit. These
circuit boards provide input/output, display, power, and control for the UDR. Each circuit board is
described in detail in the following sections and accompanied by a block diagram where applicable.
Schematic diagrams are located in Appendix B. Figure 3-2 is the system block diagram.
Main Circuit Board
The main circuit board contains the microprocessor, memory, analog output, signal input, and control
circuitry. Some of the circuitry located on the circuit board may not be installed depending on the model.
The following paragraphs explain the operation of the circuits in detail. Figure 3-3 is a block diagram of
the main circuit board.
Microprocessor
The 6802/6808 (U15) is a monolithic 8-bit microprocessor with 16 bit memory addressing. The 6802/6808
contains a crystal controlled internal clock oscillator and driver circuitry.
A 4 MHz crystal is utilized with the internal clock circuitry to obtain 1 MHz operation. The (E) enable pin on
the MPU supplies the clock for both the MPU and the rest of the system. Figure 3-4 is a typical timing
diagram for write and read cycles.
The read/write output signals the memory/peripherals that the MPU is in a read (high) state or a write (low)
state. The normal standby state is read (high).
The valid memory address (VMA) output indicates to peripheral and memory devices that there is a valid
address on the address bus.
The address bus outputs (A0 - A15) provide for addressing of external devices.
The data bus (D0 - D7) is bi-directional and is used for transferring data between the MPU and
memory/peripheral devices. The data bus will be in the output mode for a write cycle and in the input
mode for a read cycle.
The Interrupt Request Input (IRQ), when low, requests that an interrupt sequence be generated within the
MPU. The processor will wait until it completes the current instruction that is being executed before it
recognizes the request. Various internal registers are stored on the stack before a branch to the interrupt
vector is carried out. When the interrupt routine has completed, the registers are restored and the MPU
continues to execute the program. The IRQ input is not utilized on the main circuit board, however, it is
provided to the external bus connector to be used by IRQ generating devices located on the option
boards.
The reset input (active low) is used to restart the MPU from a power down condition, (restart from a power
failure or an initial start-up). A low to high transition on this input signals the MPU to begin the restart
sequence.
The non-maskable interrupt (NMI) input, upon detection of a low-going edge, requests that a non-
maskable interrupt sequence is generated within the MPU. As with the interrupt request signal, the
processor will complete the current instruction being executed before it recognizes the NMI signal. Various
internal registers are stored on the stack before a branch to the NMI vector occurs. Upon completion of
the NMI routine, the internal registers are restored and program execution continues.