Sun Microsystems Sun Fire X4100 - Manual (Page 52)

2-26 Sun Fire X4100 and Sun Fire X4200 Servers Service Manual • June 2006
2.3.4.31 BIOS Chipset Menu SouthBridge Configuration Screen
Chipset
********************************************************************************
* South Bridge Chipset Configuration * Enable/disable *
* *************************************************** * SMBUS 2.0 Controller *
* 2.0 SM Bus Controller [Enabled] * in South Bridge *
* Restore on AC/Power Loss [Power Off] * *
* Power Button Behavior [Instant Off] * *
* * *
* HT Link 0 P-Comp Mode [Auto] * *
* HT Link 0 N-Comp Mode [Auto] * *
* HT Link 0 RZ-Comp Mode [Auto] * *
* * *
* * *
* * *
* * ** Select Screen *
* * ** Select Item *
* * +- Change Option *
* * F1 General Help *
* * F10 Save and Exit *
* * ESC Exit *
* * *
* * *
********************************************************************************S
2.3.4.32 BIOS Chipset Menu PCI-X Configuration Screen
Chipset
********************************************************************************
* PCI-X Chipset Configuration * PCI clock is disabled/ *
* *************************************************** * enabled for 8131 *
* Errata 56 PCLK [Enabled] * Errata 56 if a PCI *
* HT Link 0 P-Comp Mode [Auto] * card behind 8131 *
* HT Link 0 N-Comp Mode [Auto] * bridge has more than *
* HT Link 0 RZ-Comp Mode [Auto] * 4 functions and bus *
* HT Link 1 P-Comp Mode [Auto] * speed is 133 MHz. *
* HT Link 1 N-Comp Mode [Auto] * *
* HT Link 1 RZ-Comp Mode [Auto] * *
* * *
* * *
* * *
* * ** Select Screen *
* * ** Select Item *
* * +- Change Option *
* * F1 General Help *
* * F10 Save and Exit *
* * ESC Exit *
* * *
* * *
********************************************************************************S