NEC uPD78056Y - Manual (Page 113)

113
CHAPTER 5 CPU ARCHITECTURE
BANK0
BANK1
BANK2
BANK3
FEFFH
FEF8H
FEF7H
FEE0H
HL
DE
BC
AX
H
15 0 7 0
L
D
E
B
C
A
X
16-Bit Processing 8-Bit Processing
FEF0H
FEEFH
FEE8H
FEE7H
Figure 5-22. General Register Configuration
(a) Absolute Name
(b) Function Name
BANK0
BANK1
BANK2
BANK3
FEFFH
FEF8H
FEF7H
FEE0H
RP3
RP2
RP1
RP0
R7
15 0 7 0
R6
R5
R4
R3
R2
R1
R0
16-Bit Processing 8-Bit Processing
FEF0H
FEEFH
FEE8H
FEE7H