7 block diagram – NEC uPD78056Y User Manual
Page 56
56
CHAPTER 2 OUTLINE (
µ
PD78054Y Subseries)
2.7 Block Diagram
Remarks 1. The internal ROM and RAM capacities depend on the product.
2. Pin connection in parentheses is intended for the
µ
PD78P058.
16-bit TIMER/
EVENT COUNTER
8-bit TIMER/
EVENT COUNTER 1
WATCHDOG TIMER
WATCH TIMER
SERIAL
INTERFACE 0
SERIAL
INTERFACE 1
SERIAL
INTERFACE 2
A/D CONVERTER
D/A CONVERTER
8-bit TIMER/
EVENT COUNTER 2
INTERRUPT
CONTROL
BUZZER OUTPUT
CLOCK OUTPUT
CONTROL
V
DD
V
SS
IC
(V
PP
)
78K/0
CPU CORE
ROM
RAM
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
PORT 12
PORT 13
REAL-TIME
OUTPUT PORT
EXTERNAL
ACCESS
SYSTEM
CONTROL
P00
P01-P06
P07
P10-P17
P20-P27
P30-P37
P40-P47
P50-P57
P60-P67
P70-P72
P120-P127
P130, P131
RTP0/P120-
RTP7/P127
AD0/P40-
AD7/P47
A8/P50-
A15/P57
RD/P64
WR/P65
WAIT/P66
ASTB/P67
RESET
X1
X2
XT1/P07
XT2
TO0/P30
TI00/INTP0/P00
TI01/INTP1/P01
TO1/P31
TI1/P33
TO2/P32
TI2/P34
SI0/SB0/SDA0/P25
SO0/SB1/SDA1/P26
SCK0/SCL/P27
SI1/P20
SO1/P21
SCK1/P22
STB/P23
BUSY/P24
SI2/RxD/P70
SO2/TxD/P71
SCK2/ASCK/P72
AV
DD
AV
SS
AV
REF0
ANI0/P10-
ANI7/P17
ANO0/P130,
ANO1/P131
AV
SS
AV
REF1
INTP0/P00-
INTP6/P06
BUZ/P36
PCL/P35