NEC uPD78056Y User Manual

Page 224

Advertising
background image

224

CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2

Figure 9-4. Timer Clock Select Register 1 Format

Caution

When rewriting TCL1 to other data, stop the timer operation beforehand.

Remarks 1. f

XX

: Main system clock frequency (f

X

or f

X

/2)

2. f

X

: Main system clock oscillation frequency

3. TI1

: 8-bit timer register 1 input pin

4. TI2

: 8-bit timer register 2 input pin

5. MCS : Oscillation mode selection register (OSMS) bit 0

6. Figures in parentheses apply to operation with f

X

= 5.0 MHz

TCL17 TCL16 TCL15 TCL14 TCL13 TCL12 TCL11 TCL10

7

6

5

4

3

2

1

0

Symbol

TCL1

FF41H

00H

R/W

Address

After Reset

R/W

TCL13 TCL12 TCL11 TCL10

0

0

0

0

TI1 falling edge

0

0

0

1

TI1 rising edge

0

1

1

0

0

1

1

1

f

XX

/2

f

X

/2

(2.5 MHz)

f

X

/2

2

(1.25 MHz)

1

0

0

0

f

XX

/2

2

f

X

/2

2

(1.25 MHz)

f

X

/2

3

(625 kHz)

1

0

0

1

f

XX

/2

3

f

X

/2

3

(625 kHz)

f

X

/2

4

(313 kHz)

1

0

1

0

f

XX

/2

4

f

X

/2

4

(313 kHz)

f

X

/2

5

(156 kHz)

1

0

1

1

f

XX

/2

5

f

X

/2

5

(156 kHz)

f

X

/2

6

(78.1 kHz)

1

1

0

0

f

XX

/2

6

f

X

/2

6

(78.1 kHz)

f

X

/2

7

(39.1 kHz)

1

1

0

1

f

XX

/2

7

f

X

/2

7

(39.1 kHz)

f

X

/2

8

(19.5 kHz)

1

1

1

0

f

XX

/2

8

f

X

/2

8

(19.5 kHz)

f

X

/2

9

(9.8 kHz)

1

1

1

1

f

XX

/2

9

f

X

/2

9

(9.8 kHz)

f

X

/2

10

(4.9 kHz)

MCS = 1

8-Bit Timer Register 1 Count Clock Selection

MCS = 0

Other than above

Setting prohibited

f

XX

/2

11

f

X

/2

11

(2.4 kHz)

f

X

/2

12

(1.2 kHz)

TCL17 TCL16 TCL15 TCL14

0

0

0

0

TI2 falling edge

0

0

0

1

TI2 rising edge

0

1

1

0

0

1

1

1

f

XX

/2

f

X

/2

(2.5 MHz)

f

X

/2

2

(1.25 MHz)

1

0

0

0

f

XX

/2

2

f

X

/2

2

(1.25 MHz)

f

X

/2

3

(625 kHz)

1

0

0

1

f

XX

/2

3

f

X

/2

3

(625 kHz)

f

X

/2

4

(313 kHz)

1

0

1

0

f

XX

/2

4

f

X

/2

4

(313 kHz)

f

X

/2

5

(156 kHz)

1

0

1

1

f

XX

/2

5

f

X

/2

5

(156 kHz)

f

X

/2

6

(78.1 kHz)

1

1

0

0

f

XX

/2

6

f

X

/2

6

(78.1 kHz)

f

X

/2

7

(39.1 kHz)

1

1

0

1

f

XX

/2

7

f

X

/2

7

(39.1 kHz)

f

X

/2

8

(19.5 kHz)

1

1

1

0

f

XX

/2

8

f

X

/2

8

(19.5 kHz)

f

X

/2

9

(9.8 kHz)

1

1

1

1

f

XX

/2

9

f

X

/2

9

(9.8 kHz)

f

X

/2

10

(4.9 kHz)

MCS = 1

8-Bit Timer Register 2 Count Clock Selection

MCS = 0

Other than above

Setting prohibited

f

XX

/2

11

f

X

/2

11

(2.4 kHz)

f

X

/2

12

(1.2 kHz)

Advertising