NEC uPD78056Y - Manual (Page 171)

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CHAPTER 7 CLOCK GENERATOR
MCC
CSS
CLS
Main System Clock Oscillation
Subsystem Clock Oscillation
CPU Clock
Figure 7-9. Main System Clock Stop Function (2/2)
(c) Operation when CSS is set after setting MCC with main system clock operation
7.5.2 Subsystem clock operations
When operated with the subsystem clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 1),
the following operations are carried out.
(a) The minimum instruction execution time remains constant (122
µ
s when operated at 32.768 kHz) irrespective
of bits 0 to 2 (PCC0 to PCC2) of the PCC.
(b) Watchdog timer counting stops.
Caution Do not execute the STOP instruction while the subsystem clock is in operation.
7.6 Changing System Clock and CPU Clock Settings
7.6.1 Time required for switchover between system clock and CPU clock
The system clock and CPU clock can be switched over by means of bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS)
of the processor clock control register (PCC).
The actual switchover operation is not performed directly after writing to the PCC, but operation continues on the
pre-switchover clock for several instructions (see Table 7-3).
Whether the system is operating on the main system clock or the subsystem clock can be discriminated by bit 5
(CLS) of the PCC register.