NEC uPD78056Y - Manual (Page 359)

359
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (
µ
PD78054Y Subseries)
(2) Communication operation
The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/
reception is carried out in synchronization with the serial clock.
Shift operation of the serial I/O shift register 0 (SIO0) is carried out at the falling edge of the serial clock (SCK0).
The transmitted data is held in the SO0 latch and is output from the SO0 pin. The received data input to the
SI0 pin is latched in SIO0 at the rising edge of SCK0.
Upon termination of 8-bit transfer, SIO0 operation stops automatically and the interrupt request flag (CSIIF0)
is set.
Figure 17-7. 3-Wire Serial I/O Mode Timings
The SO0 pin is a CMOS output pin and outputs current SO0 latch statuses. Thus, the SO0 pin output status
can be manipulated by setting bit 0 (RELT) and bit 1 (CMDT) of serial bus interface control register (SBIC).
However, do not carry out this manipulation during serial transfer.
Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the P27
output latch (refer to 17.4.7 SCK0/SCL/P27 pin output manipulation).
(3) Other signals
Figure 17-8 shows RELT and CMDT operations.
Figure 17-8. RELT and CMDT Operations
SI0
SCK0 1 2 3 4 5 6 7 8
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SO0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
CSIIF0
Transfer Start at the Falling Edge of SCK0
End of Transfer
RELT
CMDT
SO0 latch