NEC uPD78056Y - Manual (Page 253)

253
CHAPTER 11 WATCHDOG TIMER
11.4 Watchdog Timer Operations
11.4.1 Watchdog timer operation
When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated
to detect any runaway.
The watchdog timer count clock (runaway detection time interval) can be selected with bits 0 to 2 (TCL20 to TCL22)
of the timer clock select register 2 (TCL2).
Watchdog timer starts by setting bit 7 (RUN) of WDTM to 1. After the watchdog timer is started, set RUN to 1
within the set runaway detection time interval. The watchdog timer can be cleared and counting is started by setting
RUN to 1. If RUN is not set to 1 and the runaway detection time is past, system reset or a non-maskable interrupt
request is generated according to the WDTM bit 3 (WDTM3) value.
By setting RUN to 1, the watchdog timer can be cleared.
The watchdog timer continues operating in the HALT mode but it stops in the STOP mode. Thus, set RUN to 1
before the STOP mode is set, clear the watchdog timer and then execute the STOP instruction.
Cautions 1. The actual runaway detection time may be shorter than the set time by a maximum of
0.5 %.
2. When the subsystem clock is selected for CPU clock, watchdog timer count operation is
stopped.
Table 11-4. Watchdog Timer Runaway Detection Times
TCL22 TCL21 TCL20 Runaway Detection Time MCS = 1 MCS = 0
0 0 0 2 11 ×
1/f XX 2 11 ×
1/f X (410
µ
s) 2 12 ×
1/f X (819
µ
s)
0 0 1 2 12 ×
1/f XX 2 12 ×
1/f X (819
µ
s) 2 13 ×
1/f X (1.64 ms)
0 1 0 2 13 ×
1/f XX 2 13 ×
1/f X (1.64 ms) 2 14 ×
1/f X (3.28 ms)
0 1 1 2 14 ×
1/f XX 2 14 ×
1/f X (3.28 ms) 2 15 ×
1/f X (6.55 ms)
1 0 0 2 15 ×
1/f XX 2 15 ×
1/f X (6.55 ms) 2 16 ×
1/f X (13.1 ms)
1 0 1 2 16 ×
1/f XX 2 16 ×
1/f X (13.1 ms) 2 17 ×
1/f X (26.2 ms)
1 1 0 2 17 ×
1/f XX 2 17 ×
1/f X (26.2 ms) 2 18 ×
1/f X (52.4 ms)
1 1 1 2 19 ×
1/f XX 2 19 ×
1/f X (104.9 ms) 2 20 ×
1/f X (209.7 ms)
Remarks 1. f XX : Main system clock frequency (f X or f X /2)
2. f X : Main system clock oscillation frequency
3. MCS : Bit 0 of oscillation mode selection register (OSMS)
4. TCL20 to TCL22 : Bits 0 to 2 of timer clock select register 2 (TCL2)
5. Figures in parentheses apply to operation with f
X
= 5.0 MHz.