NEC uPD78056Y User Manual
Page 567
567
CHAPTER 27 INSTRUCTION SET
Clock
Flag
Note 1
Note 2
Z AC CY
A, #byte
2
4
–
A
←
A
∨
byte
×
saddr, #byte
3
6
8
(saddr)
←
(saddr)
∨
byte
×
A, r
Note 3
2
4
–
A
←
A
∨
r
×
r, A
2
4
–
r
←
r
∨
A
×
A, saddr
2
4
5
A
←
A
∨
(saddr)
×
A, !addr16
3
8
9 + n
A
←
A
∨
(addr16)
×
A, [HL]
1
4
5 + n
A
←
A
∨
(HL)
×
A, [HL + byte]
2
8
9 + n
A
←
A
∨
(HL + byte)
×
A, [HL + B]
2
8
9 + n
A
←
A
∨
(HL + B)
×
A, [HL + C]
2
8
9 + n
A
←
A
∨
(HL + C)
×
A, #byte
2
4
–
A
←
A
∨
byte
×
saddr, #byte
3
6
8
(saddr)
←
(saddr)
∨
byte
×
A, r
Note 3
2
4
–
A
←
A
∨
r
×
r, A
2
4
–
r
←
r
∨
A
×
A, saddr
2
4
5
A
←
A
∨
(saddr)
×
A, !addr16
3
8
9 + n
A
←
A
∨
(addr16)
×
A, [HL]
1
4
5 + n
A
←
A
∨
(HL)
×
A, [HL + byte]
2
8
9 + n
A
←
A
∨
(HL + byte)
×
A, [HL + B]
2
8
9 + n
A
←
A
∨
(HL + B)
×
A, [HL + C]
2
8
9 + n
A
←
A
∨
(HL + C)
×
A, #byte
2
4
–
A – byte
Ч Ч Ч
saddr, #byte
3
6
8
(saddr) – byte
Ч Ч Ч
A, r
Note 3
2
4
–
A – r
Ч Ч Ч
r, A
2
4
–
r – A
Ч Ч Ч
A, saddr
2
4
5
A – (saddr)
Ч Ч Ч
A, !addr16
3
8
9 + n
A – (addr16)
Ч Ч Ч
A, [HL]
1
4
5 + n
A – (HL)
Ч Ч Ч
A, [HL + byte]
2
8
9 + n
A – (HL + byte)
Ч Ч Ч
A, [HL + B]
2
8
9 + n
A – (HL + B)
Ч Ч Ч
A, [HL + C]
2
8
9 + n
A – (HL + C)
Ч Ч Ч
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access.
2. When an area except the internal high-speed RAM area is accessed.
3. Except "r = A"
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
CPU
) selected by the processor clock
control register (PCC).
2. This clock cycle applies to internal ROM program.
3. n is the number of waits when external memory expansion area is read from.
Mnemonic
Operands
Byte
Operation
Instruction
Group
OR
XOR
CMP
8-bit
operation