NEC uPD78056Y - Manual (Page 373)

373
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (
µ
PD78054Y Subseries)
(b) Serial bus interface control register (SBIC)
SBIC is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets SBIC to 00H.
R/W RELT Use for stop condition output. When RELT = 1, SO0 latch is set to 1. After SO0 latch setting, automatically
cleared to 0. Also cleared to 0 when CSIE0 = 0.
R/W CMDT Use for start condition output. When CMDT = 1, SO0 latch is cleared to 0. After clearing SO0 latch,
automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
R RELD Stop Condition Detection
0 Clear Conditions
• When transfer start instruction is executed
• If SIO0 and SVA values do not match in address reception
• When CSIE0 = 0
• When RESET input is applied
1 Setting Condition
• When stop condition is detected
R CMDD Start Condition Detection
0 Clear Conditions
• When transfer start instruction is executed
• When stop condition is detected
• When CSIE0 = 0
• When RESET input is applied
1 Setting Condition
• When start condition is detected
R/W ACKT SDA0 (SDA1) is set to low after the Set instruction execution (ACKT = 1) before the next SCL falling edge.
Used for generating an ACK signal by software if the 8-clock wait mode is selected. Cleared to 0 if CSIE =
0 when a transfer by the serial interface is started.
Note Bits 2, 3, and 6 (RELD, CMDD, ACKD) are read-only bits.
Remarks 1. Bits 0, 1, and 4 (RELT, CMDT, ACKT) are 0 when read after the data is set.
2. CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
(continued)
<6> <5> <4> <3> <2> <1> <0> <7>
Symbol
SBIC BSYE ACKD ACKE FF61H 00H R/W Note
Address After Reset R/W
ACKT CMDD RELD CMDT RELT