NEC uPD78056Y - Manual (Page 530)

530
CHAPTER 23 STANDBY FUNCTION
23.2.2 STOP mode
(1) STOP mode set and operating status
The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock.
Cautions 1. When the STOP mode is set, the X2 pin is internally connected to V
DD
via a pull-up resistor
to minimize the leakage current at the crystal oscillator. Thus, do not use the STOP mode
in a system where an external clock is used for the main system clock.
2. Because the interrupt request signal is used to clear the standby mode, if there is an
interrupt source with the interrupt request flag set and the interrupt mask flag reset, the
standby mode is immediately cleared if set. Thus, the STOP mode is reset to the HALT
mode immediately after execution of the STOP instruction. After the wait set using the
oscillation stabilization time select register (OSTS), the operating mode is set.
The operating status in the STOP mode is described below.
Table 23-3. STOP Mode Operating Status
Setting of STOP Mode
With subsystem clock Without subsystem clock
Item
Clock generator Only main system clock stops oscillation.
CPU Operation stops.
Port (output latch) Status before STOP mode setting is held.
16-bit timer/event counter Operable when watch timer output is Operation stops.
selected as count clock (f XT is selected as
count clock of watch timer)
8-bit timer/event counter Operable when TI1 and TI2 are selected for the count clock.
Watch timer Operable when f
XT
is selected for the Operation stops.
count clock.
Watchdog timer Operation stops.
A/D converter
D/A converter Operable.
Real-time output port Operable when external trigger is used or TI1 and TI2 are selected for the 8-bit
timer/event counter count clock.
Serial interface Other than Operable when externally supplied clock is specified as the serial clock.
automatic
transmit/receive
function and
UART
Automatic Operation stops.
transmit/receive
function and
UART
External interrupt INTP0 Not operable.
INTP1-INTP6 Operable.
Bus line for AD0-AD7 High impedance.
external
A0-A15 Status before STOP mode setting is held.
expansion
ASTB Low level.
WR, RD High level.
WAIT High impedance.