NEC uPD78056Y User Manual
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
µ
PD78054 Subseries)
(10) Discrimination of slave busy state
When device is in the master mode, follow the procedure below to judge whether slave device is in the busy
state or not.
<1> Detect acknowledge signal (ACK) or interrupt request signal generation.
<2> Set the port mode register PM25 (or PM26) of the SB0/P25 (or SB1/P26) pin into the input mode.
<3> Read out the pin state (when the pin level is high, the READY state is set).
After the detection of the READY state, set the port mode register to 0 and return to the output mode.
(11) SBI mode precautions
(a) Slave selection/non-selection is detected by match detection of the slave address received after bus
release (RELD = 1).
For this match detection, match interrupt (INTCSI0) of the address to be generated with WUP = 1 is
normally used. Thus, execute selection/non-selection detection by slave address when WUP = 1.
(b) When detecting selection/non-selection without the use of interrupt with WUP = 0, do so by means of
transmission/reception of the command preset by program instead of using the address match detection
method.
(c) A transition of the SB0 (SB1) pin from low to high or high to low while the SCK0 line is high is interpreted
as a bus release or command signal. Therefore, a shift in the change timing of the bus due to the influence
of the board capacitance, etc., may be incorrectly identified as a bus release signal (or command signal),
regardless of whether data is being transmitted. For this reason, special care must be taken regarding
wiring.
(d) For pins which are to be used for data input/output, be sure to carry out the following settings before serial
transfer of the 1st byte after RESET input.
<1> Set the P25 and P26 output latches to 1.
<2> Set bit 0 (RELT) of the serial bus interface control register (SBIC) to 1.
<3> Reset the P25 and P26 output latches from 1 to 0.
(e) If SB0 (SB1) line changes from low level to high level or from high level to low level while SCK0 line is
high level, it is recognized as a bus release signal or a command signal. Therefore, if a lag of changing
timing occurs on the bus because of the substrate capacity, etc., it may be judged as a bus release signal
(command signal) despite that data is being transmitted. Exercise care for wiring.