NEC uPD78056Y - Manual (Page 168)

168
CHAPTER 7 CLOCK GENERATOR
7.4.3 Scaler
The scaler divides the main system clock oscillator output (f
XX
) and generates various clocks.
7.4.4 When no subsystem clocks are used
If it is not necessary to use subsystem clocks for low power consumption operations and clock operations,
connect the XT1 and XT2 pins as follows.
XT1 : Connect to V
DD
.
XT2 : Leave open.
In this state, however, some current may leak via the internal feedback resistor of the subsystem clock oscillator
when the main system clock stops. To suppress the leakage current, disconnect the above internal feedback resistor
by using the bit 6 (FRC) of the processor clock control register (PCC). In this case also, connect the XT1 and XT2
pins as described above.