NEC uPD78056Y - Manual (Page 536)

536
CHAPTER 24 RESET FUNCTION
Table 24-1. Hardware Status after Reset (2/2)
Hardware Status after Reset
Watch timer Mode control register (TMC2) 00H
Clock select register (TCL2) 00H
Mode register (WDTM) 00H
Clock select register (TCL3) 88H
Shift registers (SIO0, SIO1) Undefined
Mode registers (CSIM0, CSIM1, CSIM2) 00H
Serial bus interface control register (SBIC) 00H
Slave address register (SVA) Undefined
Automatic data transmit/receive control register (ADTC) 00H
Automatic data transmit/receive address pointer (ADTP) 00H
Automatic data transmit/receive interval specify register (ADTI) 00H
Asynchronous serial interface mode register (ASIM) 00H
Asynchronous serial interface status register (ASIS) 00H
Baud rate generator control register (BRGC) 00H
Transmit shift register (TXS)
Receive buffer register (RXB)
Interrupt timing specify register (SINT) 00H
A/D converter Mode register (ADM) 01H
Conversion result register (ADCR) Undefined
Input select register (ADIS) 00H
D/A converter Mode register (DAM) 00H
Conversion value setting register (DACS0, DACS1) 00H
Real-time output port Mode register (RTPM) 00H
Control register (RTPC) 00H
Buffer register (RTBL, RTBH) 00H
ROM correction (Note) Correction address register (CORAD0, CORAD1) 0000H
Correction control register (CORCN) 00H
Request flag register (IF0L, IF0H, IF1L) 00H
Mask flag register (MK0L, MK0H, MK1L) FFH
Priority specify flag register (PR0L, PR0H, PR1L) FFH
External interrupt mode register (INTM0, INTM1) 00H
Key return mode register (KRM) 02H
Sampling clock select register (SCS) 00H
Watchdog timer
Serial interface
FFH
Interrupt
Note Provided only in the
µ
PD78058, 78058Y, 78P058, 78P058Y.