NEC uPD78056Y User Manual
Page 565
565
CHAPTER 27 INSTRUCTION SET
Clock
Flag
Note 1
Note 2
Z AC CY
rp, #word
3
6
–
rp
←
word
saddrp, #word
4
8
10
(saddrp)
←
word
sfrp, #word
4
–
10
sfrp
←
word
AX, saddrp
2
6
8
AX
←
(saddrp)
saddrp, AX
2
6
8
(saddrp)
←
AX
MOVW
AX, sfrp
2
–
8
AX
←
sfrp
sfrp, AX
2
–
8
sfrp
←
AX
AX, rp
Note 3
1
4
–
AX
←
rp
rp, AX
Note 3
1
4
–
rp
←
AX
AX, !addr16
3
10
12 + 2n AX
←
(addr16)
!addr16, AX
3
10
12 + 2m (addr16)
←
AX
XCHW
AX, rp
Note 3
1
4
–
AX
↔
rp
A, #byte
2
4
–
A, CY
←
A + byte
Ч Ч Ч
saddr, #byte
3
6
8
(saddr), CY
←
(saddr) + byte
Ч Ч Ч
A, r
Note 4
2
4
–
A, CY
←
A + r
Ч Ч Ч
r, A
2
4
–
r, CY
←
r + A
Ч Ч Ч
A, saddr
2
4
5
A, CY
←
A + (saddr)
Ч Ч Ч
A, !addr16
3
8
9 + n
A, CY
←
A + (addr16)
Ч Ч Ч
A, [HL]
1
4
5 + n
A, CY
←
A + (HL)
Ч Ч Ч
A, [HL + byte]
2
8
9 + n
A, CY
←
A + (HL + byte)
Ч Ч Ч
A, [HL + B]
2
8
9 + n
A, CY
←
A + (HL + B)
Ч Ч Ч
A, [HL + C]
2
8
9 + n
A, CY
←
A + (HL + C)
Ч Ч Ч
A, #byte
2
4
–
A, CY
←
A + byte + CY
Ч Ч Ч
saddr, #byte
3
6
8
(saddr), CY
←
(saddr) + byte + CY
Ч Ч Ч
A, r
Note 4
2
4
–
A, CY
←
A + r + CY
Ч Ч Ч
r, A
2
4
–
r, CY
←
r + A + CY
Ч Ч Ч
A, saddr
2
4
5
A, CY
←
A + (saddr) + CY
Ч Ч Ч
A, !addr16
3
8
9 + n
A, CY
←
A + (addr16) + CY
Ч Ч Ч
A, [HL]
1
4
5 + n
A, CY
←
A + (HL) + CY
Ч Ч Ч
A, [HL + byte]
2
8
9 + n
A, CY
←
A + (HL + byte) + CY
Ч Ч Ч
A, [HL + B]
2
8
9 + n
A, CY
←
A + (HL + B) + CY
Ч Ч Ч
A, [HL + C]
2
8
9 + n
A, CY
←
A + (HL + C) + CY
Ч Ч Ч
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access.
2. When an area except the internal high-speed RAM area is accessed.
3. Only when rp = BC, DE or HL
4. Except "r = A"
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
CPU
) selected by the processor clock
control register (PCC).
2. This clock cycle applies to internal ROM program.
3. n is the number of waits when external memory expansion area is read from.
4. m is the number of waits when external memory expansion area is written to.
Mnemonic
Operands
Byte
Operation
Instruction
Group
16-bit
data
transfer
ADD
ADDC
8-bit
operation