Altera Floating-Point - Manual (Page 103)

Table 14-1: ALTFP_SINCOS Resource Utilization and Performance
Device Family Function Precision
Output
Latency
Logic usage
f
MAX
(MHz)
Adaptive
Look-Up
Tables
(ALUTs)
Dedicate
d Logic
Registers
(DLRs)
Adaptive
Logic
Modules
(ALMs)
18-Bit
DSP
Stratix IV
Sine Single 36 2,859 2,190 1,830 16 292.96
Cosine Single 35 2,753 2,041 1,745 16 258.26
ALTFP_SINCOS Signals
Figure 14-1: ALTFP_SINCOS Signals
data[31..0]
aclr
ALTFP_SINCOS
result[31..0]
clk_en
clock
Table 14-2: ALTFP_SINCOS IP Core Input Signals
Port Name Required Description
aclr
No Asynchronous clear. When the
aclr
port is asserted high, the function
is asynchronously cleared.
clk_en
No Clock enable. When the
clk_en
port is asserted high, sine or cosine
operation takes place. When the signal is asserted low, no operation
occurs and the outputs remain unchanged.
clock
Yes Clock input to the megafunction.
data[]
Yes Floating-point input data. The MSB is the sign bit, the next MSBs are
the exponent, and the LSBs are the mantissa. This input port size is the
total width of the sign bit, exponent bits, and mantissa bits.
14-2 ALTFP_SINCOS Signals
UG-01058
2014.12.19
Altera Corporation ALTFP_SINCOS IP Core
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