Altera Floating-Point - Manual (Page 19)

• Support for floating-point formats.
• Input support for not-a-number (NaN), infinity, zero, and normal numbers.
• Optional asynchronous input ports including asynchronous clear (
aclr
) and clock enable (
clk_en
).
• Support for round-to-nearest-even rounding mode.
• Compute results of any mathematical operations according to the IEEE-754 standard compliance with
a maximum of 1 unit in the last place (u.l.p.) error. This assumption is applied to all floating-point IP
cores excluding complex matrix multiplication and inverse operations (for example,
ALTFP_MATRIX_MULTI and ALFP_MATRIX_INV), where a slight increase in errors is observed
due to the accumulation of errors during the mathematical operation.
Altera floating-point IP cores do not support denormal number inputs. If the input is a denormal value,
the IP core forces the value to zero and treats the value as a zero before going through any operation.
Related Information
FFT MegaCore Function User Guide
Altera also offers the single-precision floating-point option in the FFT MegaCore.
IEEE-754 Standard for Floating-Point Arithmetic
The floating-point IP cores implement the following representations in the IEEE-754 standard:
• Floating-point numbers
• Special values (zero, infinity, denormal numbers, and NaN bit combinations)
• Single-precision, double-precision, and single-extended precision formats for floating-point numbers
Floating-Point Formats
All floating-point formats have binary patterns. In Figure 1–1, S represents a sign bit, E represents an
exponent field, and M is the mantissa (part of a logarithm, or fraction) field.
For a normal floating-point number, a leading 1 is always implied, for example, binary 1.0011 or
decimal 1.1875 is stored as 0011 in the mantissa field. This format saves the mantissa field from using an
extra bit to represent the leading 1. However, the leading bit for a denormal number can be either 0 or 1.
For zero, infinity, and NaN, the mantissa field does not have an implied leading 1 nor any explicit leading
bit.
Figure 1-8: IEEE-754 Floating-Point Format
This figure shows a floating-point format.
S E M
Single-Precision Format
The single-precision format contains the following binary patterns:
• The MSB holds the sign bit.
• The next 8 bits hold the exponent bits.
• 23 LSBs hold the mantissa.
The total width of a floating-point number in the single-precision format is 32 bits. The bias for the
single-precision format is 127.
UG-01058
2014.12.19
IEEE-754 Standard for Floating-Point Arithmetic 1-13
About Floating-Point IP Cores Altera Corporation
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