Altera Floating-Point - Manual (Page 108)

Figure 15-2: ALTFP_ABS Signals
data[]
overflow_in
nan_in
division_by_zero_in
zero_in
underflow_in
clk_en
clock
inst
ALTFP_ABS
result[]
overflow
nan
underflow
zero
division_by_zero
aclr
Table 15-3: ALTFP_ABS Input Signals
Port Name Required Description
aclr
No Asynchronous clear. When the
aclr
port is asserted high, the
function is asynchronously cleared.
clk_en
No Clock enable. When the
clk_en
port is asserted high, an
absolute value operation takes place. When the signal is
asserted low, no operation occurs and the outputs remain
unchanged.
clock
Yes Clock input to the IP core.
data[]
Yes Floating-point input data. The MSB is the sign bit, the next
MSBs are the exponent, and the LSBs are the mantissa. This
input port size is the total width of sign bit, exponent bits,
and mantissa bits.
zero_in
No Zero exception input. Carry-through exception input port
from other floating-point modules.
nan_in
No NaN exception input. Carry-through exception input port
from other floating-point modules.
overflow_in
No Overflow exception input. Carry-through exception input
port from other floating-point modules.
underflow_in
No Underflow exception input. Carry-through exception input
port from other floating-point modules.
division_by_zero_
in
No Division-by-zero exception input. Carry-through exception
input port from other floating-point modules.
15-4 ALTFP_ABS Signals
UG-01058
2014.12.19
Altera Corporation ALTFP_ABS IP Core
Send Feedback