Altera Floating-Point - Manual (Page 65)

Table 7-3: ALTFP_MULT Resource Utilization and Performance for Stratix IV Devices with Dedicated
Multiplier Circuitry
Device Family Precision
Output
latency
Logic usage
f
MAX
(MHz)
Adaptive
Look-Up
Tables
(ALUTs)
Dedicated
Logic
Registers
(DLRs)
Adaptive
Logic
Modules
(ALMs)
18-bit DSP
Stratix IV
Single
5 138 148 100 4 274
11 185 301 190 4 445
Double
5 306 367 272 10 255
11 419 523 348 10 395
ALTFP_MULT Design Example: Multiplication of Double-Precision Format
Numbers
This design example uses the ALTFP_MULT IP core to compute the multiplication results of two double-
precision format numbers. This example uses the parameter editor GUI to define the core.
Related Information
• Floating-Point IP Cores Design Example Files on page 1-16
• Floating-Point IP Cores Design Examples
Provides the design example files for the Floating-Point IP cores
• ModelSim-Altera Software Support
Provides information about installation, usage, and troubleshooting
ALTFP_MULT Design Example: Understanding the Simulation Waveform
The simulation waveform in this design example is not shown in its entirety. Run the design example files
in the ModelSim-Altera software to see the complete simulation waveforms.
Figure 7-1: ALTFP_MULT Simulation Waveform
This figure shows the expected simulation results in the ModelSim-Altera software.
UG-01058
2014.12.19
ALTFP_MULT Design Example: Multiplication of Double-Precision Format Numbers 7-3
ALTFP_MULT IP Core Altera Corporation
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