Altera Floating-Point - Manual (Page 149)

Family
Input
Width
Input
Fractio
n
Output
Precisi
on
Latenc
y
f
MAX
ALMs M10K M20K
DSP
Blocks
Logic Registers
Primar
y
Secondary
Stratix
V
(5SGXE
A7K2F4
0C2)
32 0 Single 3 579.71 148 -- 0 0 97 1
32 0 Doubl
e
2 547.95 161 -- 0 0 72 1
32 16 Single 3 550.66 148 -- 0 0 97 1
32 16 Doubl
e
2 536.19 160 -- 0 0 72 0
32 32 Single 3 558.66 145 -- 0 0 96 1
32 32 Doubl
e
2 496.28 154 -- 0 0 72 1
64 0 Single 3 454.55 194 -- 0 0 125 0
64 0 Doubl
e
3 434.22 304 -- 0 0 194 3
64 16 Single 3 454.55 194 -- 0 0 125 0
64 16 Doubl
e
3 434.22 304 -- 0 0 194 3
64 32 Single 3 454.55 194 -- 0 0 125 0
64 32 Doubl
e
3 434.22 304 -- 0 0 194 3
18-22 ALTERA_FP_FUNCTIONS Resource Utilization and Performance
UG-01058
2014.12.19
Altera Corporation ALTERA_FP_FUNCTIONS IP Core
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