Altera Floating-Point - Manual (Page 82)

DATA[] SIGN BIT RESULT[] Underflow Zero Division_by_
zero
NaN
Normal 0/1 Denormal 1 1 0 0
Normal 0/1 Infinity 0 0 0 0
Normal 0/1 Zero 1 1 0 0
Denormal 0/1 Infinity 0 0 1 0
Zero 0/1 Infinity 0 0 1 0
Infinity 0/1 Zero 0 1 0 0
NaN X NaN 0 0 0 1
ALTFP_INV Resource Utilization and Performance
This table lists the resource utilization and performance information for the ALTFP_INV IP core. The
information was derived using the Quartus II software version 10.0.
Table 10-2: ALTFP_INV Resource Utilization and Performance for Stratix IV Devices
Device Family Precision
Output
Latency
Logic usage
f
MAX
(MHz)
Adaptive
Look-Up
Tables
(ALUTs)
Dedicated
Logic
Registers
(DLRs)
Adaptive
Logic
Modules
(ALMs)
18-Bit DSP
Stratix IV
Single 20 401 616 373 16 412
Double 27 939 1,386 912 48 203
ALTFP_INV Design Example: Inverse of Single-Precision Format Numbers
This design example uses the ALTFP_INV IP core to compute the inverse of single-precision format
numbers. This example uses the parameter editor in the Quartus II software.
Related Information
• Floating-Point IP Cores Design Example Files on page 1-16
• Floating-Point IP Cores Design Examples
Provides the design example files for the Floating-Point IP cores
• ModelSim-Altera Software Support
Provides information about installation, usage, and troubleshooting
(3) Any calculated or computed denormal output is replaced by a zero and asserts the zero and underflow flags.
(4) Any denormal input is treated as a zero before going through the inverse process.
10-2 ALTFP_INV Resource Utilization and Performance
UG-01058
2014.12.19
Altera Corporation ALTFP_INV IP Core
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