Altera Interlaken MegaCore Function User Manual
User guide interlaken megacore function
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101 Innovation Drive
San Jose, CA 95134
UG-01092-1.3
User Guide
Interlaken MegaCore Function
Document last updated for Altera Complete Design Suite version:
Document publication date:
12.0
June 2012
Interlaken MegaCore Function User Guide
c
The Interlaken MegaCore function is scheduled for product
obsolescence and discontinued support as described in
Therefore, Altera does not recommend use of this IP
in new designs. For more information about Altera’s current IP
offering, refer to Altera’s
website.
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Table of contents
Document Outline
- Interlaken MegaCore Function User Guide
- Contents
- 1. About This MegaCore Function
- 2. Getting Started
- 3. Parameter Settings
- 4. Functional Description
- Architecture Overview
- Interfaces Overview
- Clocking and Reset Structure
- Transmit Path
- Receive Path
- Calendar and Status Block
- High-Speed I/O Block
- Out-of-Band Flow Control Block
- 5. Signals
- 6. Qsys Design Examples
- A. Initializing the Interlaken MegaCore Function
- B. Excluding Transceivers for Faster Simulation
- C. Closing Timing on 10- and 20-lane Designs
- D. Porting an Interlaken Design from the Previous Version of the Software
- Additional Information