Altera Interlaken MegaCore Function - Manual (Page 67)

Chapter 6: Qsys Design Examples 6–5
Running a Design Example
June 2012 Altera Corporation Interlaken MegaCore Function
User Guide
2. Change directory to the testbench subdirectory of your design example working
directory, alt_interlaken_8lane_6g/testbench.
3. Type the following command at the ModelSim command prompt:
do run_simulation.do
r
The design example runs and displays a waveform showing the signals as the
design example implements the sequence described in
“Design Example
Simulation Sequence” on page 6–3 .
The simulation run completes successfully with the following message:
# Test complete
# Received 100 packets on channel 0
# Received 100 packets on channel 1
# Simulation success...
1 When simulation completes, you are prompted to quit the ModelSim
software. If the Modelsim Transcript tab is not currently active, click No
and then click the Transcript tab to view the transcript and ensure the
preceding message appears.
4. On the File menu, click Quit to close the ModelSim software and return to the
Quartus II software to compile your system.
Compiling and Programming the Device
The Qsys system files are now ready for compilation in the Quartus II software. If you
have acquired a license for this design example variation, compilation generates an
.sof
for device programming. To compile your system design in the Quartus II
software, perform the following steps:
1. Open the Quartus II project you created in “Creating the Quartus II Project and
Generating the Qsys System” on page 6–4 .
2. On the Processing menu, click Start Compilation to compile your system.
After you compile the design example, you can program your target Altera device
and verify the design in hardware using the appropriate Interlaken MegaCore
function license.
The alt_interlaken_20lane_6g design example requires some additional steps to
ensure it achieves timing closure. Refer to
Appendix C, Closing Timing on 10- and
20-lane Designs for a list of steps you can implement to improve timing.