Altera Interlaken MegaCore Function - Manual (Page 81)

June 2012 Altera Corporation Interlaken MegaCore Function
User Guide
C. Closing Timing on 10- and 20-lane
Designs
I/O timing is critical for Interlaken MegaCore functions. Achieving timing closure for
10- and 20-lane Interlaken MegaCore function designs can be difficult, because these
variations use the transceivers in Basic (PMA Direct) mode, in which the transceiver
block PCS blocks are not utilized.
This appendix provides guidance to help achieve timing closure for your 20-lane
Interlaken MegaCore function. You can adapt these steps for different locations and
region sizes if you are having difficulty closing timing for your 10-lane Interlaken
MegaCore function.
The steps described in this appendix use the Quartus II software LogicLock™ feature
to lock the Interlaken MegaCore function on the left edge of the Stratix IV GX device
and ensure that the various blocks are shaped so that all the transceiver assignments
are on the same edge. After you use the LogicLock feature to lock the Interlaken IP
core in a set location on the device, you compile your design and start working to
close timing on the remaining failing paths identified by the TimeQuest Timing
Analyzer.
To help close the timing gap for your 20-lane Interlaken MegaCore function, perform
the following steps before compiling your design:
1. In the Quartus II software, on the File menu, click Open Project and select your
Quartus II project.
2. On the Processing menu, point to Start and click Analysis & Synthesis. Analysis
and synthesis may take several minutes.
3. After Analysis and Synthesis completes, on the Assignments menu, click
LogicLock Regions Window . The LogicLock Regions window opens.
4. To create LogicLock regions for the RX and TX paths, perform the following steps:
a. In the Compilation Hierarchy window, navigate to the top level of the
Interlaken RX hierarchy, <instance name>:irx.
b. Right-click the top level of the Interlaken RX hierarchy, select LogicLock
Region , and click Create New LogicLock Region. The new LogicLock region
appears in the LogicLock Regions window.
c. Repeat steps a and b for the Interlaken TX hierarchy, <instance name>:itx.
5. To set the parameters of the new Interlaken RX hierarchy LogicLock region,
perform the following steps:
a. In the LogicLock Regions window, right-click the new RX hierarchy LogicLock
region row, and click LogicLock Regions Properties.
b. On the Size & Origin tab, under Size, turn off Auto and set the Width to 55
and the Height to 64.
c. Under Origin, turn off Floating and set Location string to X7_Y64.
d. Click Apply.
e. Click OK.