Altera Interlaken MegaCore Function - Manual (Page 21)

Chapter 2: Getting Started 2–9
Compiling the Full Design and Programming the FPGA
June 2012 Altera Corporation Interlaken MegaCore Function
User Guide
2. For each N, perform the following steps:
a. In the <<new>> cell in the To column, type the top-level signal name for your
Interlaken MegaCore function instance rx_serial_dataN_export signal.
b. Double-click in the Assignment Name column and click I/O Standard.
c. Double-click in the Value column and click 1.4-V PCML.
3. Repeat step 2 for your Interlaken MegaCore function instance
tx_serial_dataN_export signals.
Compiling the Full Design and Programming the FPGA
You can use the Start Compilation command on the Processing menu in the
Quartus II software to compile your design.
The 10- and 20-lane Interlaken MegaCore function variations require fine tuning to
achieve timing closure. Refer to
Appendix C, Closing Timing on 10- and 20-lane
Designs for a list of steps you can implement to improve timing.
After successfully compiling your design, program the target Altera device with the
Programmer and verify the design in hardware. Programming the device requires
that you have a license for your Interlaken MegaCore function variation. Refer to
“Interlaken MegaCore Function Licenses” on page 1–5 .
f
For Information About Refer To
Compiling your design
Quartus II Incremental Compilation for Hierarchical and Team-
Based Design
chapter in volume 1 of the Quartus II Handbook
Programming the device
Quartus II Programmer chapter in volume 3 of the Quartus II
Handbook