Altera Interlaken MegaCore Function - Manual (Page 70)

A–2 Appendix A: Initializing the Interlaken MegaCore Function
Troubleshooting an Interlaken Link
Interlaken MegaCore Function June 2012 Altera Corporation
User Guide
4. After both rx_status_all_word_locked and rx_status_all_sync_locked are
asserted, the rx_status_fully_locked signal is asserted. This signal indicates lane
alignment and meta frame alignment are complete, and the Interlaken receiver is
fully locked. This state is RX Operational, shown in Figure 9 in the Interlaken
Protocol Definition, Revision 1.2.
The rx_status_fully_locked signal is asserted four meta frames after the
rx_status_all_word_locked
and rx_status_all_sync_locked signals are
asserted. All of the signals are expected to remain high after they are first asserted
during initialization.
Now your Interlaken IP core is ready to start sending and receiving packets.
1 The TX status signals might toggle during initialization.Their values are not valid
until after initialization completes, when the rx_status_fully_locked signal is
asserted. By default, an internal parameter setting ensures that the TX FIFO never
underflows, so the application can choose to monitor or to ignore the
tx_status_hungry
and tx_status_underflow signals. During initialization, the
application should ignore all the TX status signals. Refer to Table 5–3 on page 5–4 .
Troubleshooting an Interlaken Link
If your application cannot establish an Interlaken link, check for the following
symptoms that indicate specific potential root causes:
■ If the rx_status_per_lane_word_lock[i] signal is not asserted for some lane i,
this lane has not achieved word lock. The RX lanes can establish word lock in the
presence of very high bit error rates, so bit errors are unlikely to be the cause of the
problem. Instead, focus on the consistency between your MegaCore function data
rate and the different clock rates, and whether you have an extreme cabling error
such as TX-RX reversal. For information about the recommended clock rates for
different Interlaken data rates, refer to
“Clocking and Reset Structure” on
page 4–5 .
■ If the rx_status_per_lane_sync_lock[i] signal is not asserted for some lane i,
this lane has not achieved meta frame lock or has not recovered the scrambler seed
successfully. Meta frame lock requires a moderate quality connection to the
transceiver. If the lane does not achieve lock, check that the same meta frame
length is specified for the two Interlaken link partners, and that the cables that
connect to your board’s transceiver pins meet the requirements of your board
specification. If the lock is intermittent, recheck the physical connection of the link
cables to the transceiver, and confirm that the analog settings of the transceiver
remain at the default values for the Interlaken MegaCore function.
■ If the value of rx_status_per_lane_crc32_errs is high for any lane, while
rx_status_per_lane_sync_lock
remains asserted, the lane is experiencing
CRC-32 errors. Because the lane achieved meta frame lock, you can rule out gross
physical connection issues. Instead, focus on analog signal integrity causes.