Altera Interlaken MegaCore Function - Manual (Page 48)

4–22 Chapter 4: Functional Description
High-Speed I/O Block
Interlaken MegaCore Function June 2012 Altera Corporation
User Guide
The calendar and status block sends the RX calendar bits to the enable logic for the
arbiter. These bits contain the XON/XOFF status for the channels in the Interlaken
link partner.
Behavior with Exposed Calendar Ports
If you turn on Expose calendar ports in the Interlaken parameter editor, the calendar
and status block provides the RX calendar bits to the application on the
rx_status_calendar
bus, and receives the TX calendar bits from the application on
the tx_control_status_calendar bus rather than from the lane status block. The
calendar and status block sends the RX calendar bits to the enable logic for the arbiter,
as it does when calendar ports are not exposed, but the application controls any
additional use of these bits. The arbiter enable logic interprets RX calendar bits 0 and 1
as XON/XOFF status for the two channels, exactly as it does when calendar ports are
not exposed. However, you can modify the RTL to change this behavior, in addition to
using the exposed RX calendar ports in any way you choose.
In this case, you can specify 1, 8, or 16 pages of 16 calendar bits in the Interlaken
parameter editor. The Interlaken MegaCore function receives in-band flow control
bits in the control words from the Interlaken link, and makes them available to the
application on the rx_status_calendar output signals. The MegaCore function
receives outgoing in-band flow control bits from the application on the
tx_control_tx_calendar
signal, and inserts them in bits [55:40] of the outgoing
control words, as required by the Interlaken specification. The Interlaken MegaCore
function does not insert any in-band flow control calendar bits in the multiple-use bits
[31:24] of the outgoing control words.
For information about the rx_status_calendar and tx_control_status_calendar
signals, refer to
Table 5–6 on page 5–5 and Table 5–8 on page 5–7 .
Status Counters
The status counters count the time and the number of CRC-24 errors encountered so
far since the RX Operational state was achieved. The time counter increments every
318 × 10
6 rx_mac_c_clk cycles. The locked time appears on the
rx_status_locked_time status signal bus.
For information about the individual output status signals, refer to Table 5–2 on
page 5–3 .
High-Speed I/O Block
The high-speed I/O (HSIO) block comprises multiple ALTGX megafunction blocks
and an optional FIFO and pipeline registers block. The FIFO and pipeline registers
block is instantiated only when the ALTGX megafunction operates in PMA Direct
mode. The ALTGX megafunction is configured in PMA Direct mode in 10- and
20-lane Interlaken MegaCore function variations, and in low latency PCS mode in the
other variations.