Altera Interlaken MegaCore Function - Manual (Page 74)

B–2 Appendix B: Excluding Transceivers for Faster Simulation
External Transceiver Interface Clocks
Interlaken MegaCore Function June 2012 Altera Corporation
User Guide
Figure B–1 illustrates how the external transceiver interface is derived from the full
Interlaken MegaCore function.
This appendix describes the external transceiver interface.
External Transceiver Interface Clocks
If you turn on Exclude transceivers, your Interlaken MegaCore function exposes the
interface to the transceivers. With this parameter setting, the Interlaken MegaCore
function has the following external transceiver interface input clocks:
■ rx_lane_clkN_export[M:0] —these (N × M) input clocks each clock a distinct
Interlaken receive lane. The Interlaken MegaCore function derives an RX PCS
block clock from these input clocks.
The grouping of these clocks indicated by the use of N and M is based on the
connections to transceivers when they are included: N is the number of transceiver
blocks required for this variation (minus 1), and M is the number of lanes per
transceiver block (minus 1). For the 10-lane and 20-lane variations, M is five. For
the remaining variations, M is four. For an illustration of this numbering scheme,
refer to
“Clock Diagrams for the Interlaken MegaCore Function” on page 4–6 .
■ tx_lane_c_clk —clocks the TX PCS block and the Interlaken transmit lanes.
Figure B–1. Interlaken MegaCore Function Block Diagram Showing the External Transceiver Interface
Interlaken MegaCore Function
Application
Interface
T
ransceiv
er Bloc
k
s
TX
PCS
TX
MAC
RX
PCS
RX
MAC
TX Out-of-Band
Flow Control
RX Out-of-Band
Flow Control
Calendar
and
Status
Filter
and
Buffer
Filter
and
Buffer
Packet
Regroup
Individual
Reset Signals
Packet
Regroup
Arbiter
Channel 0
Channel 1
Channel 0
Channel 1
Calendar and
lane, link status
OOB FC Block
Interlaken
Link
External
Transceiver
Interface
Out-of-Band
Flow Control
Interface