Altera SerialLite III Streaming MegaCore Function - Manual (Page 15)

Note: If your design targets Arria 10 devices, the transceiver reconfiguration functionality is embedded
inside the transceivers. The
phy_mgmt
bus interface connects directly to the Avalon-MM dynamic
reconfiguration interface of the embedded Arria 10 Native PHY IP core. This interface is provided
at the top level.
Files Generated for Altera IP Cores
The Quartus II software generates the following IP core output file structure:
Figure 3-2: IP Core Generated Files
<your_testbench>_tb.csv
<your_testbench>_tb.spd
<your_ip>.cmp - VHDL component declaration file
<your_ip>.ppf - XML I/O pin information file
<your_ip>.qip - Lists IP synthesis files
<your_ip>.sip - Contains assingments for IP simulation files
<your_ip>.v or .vhd
Top-level IP synthesis file <your_ip>.v or .vhd
Top-level simulation file
<simulator_setup_scripts>
<your_ip>.qsys - System or IP integration file
<your_ip>_bb.v - Verilog HDL black box EDA synthesis file
<your_ip>_inst.v or .vhd - Sample instantiation template
<your_ip>_generation.rpt - IP generation report
<your_ip>.debuginfo - Contains post-generation information
<your_ip>.html - Connection and memory map data
<your_ip>.bsf - Block symbol schematic
<your_ip>.spd - Combines simulation scripts for multiple cores
<your_ip>_tb.qsys
Testbench system file
<your_ip>.sopcinfo - Software tool-chain integration file
<project directory>
<EDA tool setup
scripts>
<your_ip>
IP variation files
<testbench>_tb
testbench system
sim
Simulation files
synth
IP synthesis files
sim
simulation files
<EDA tool name>
Simulator scripts
<testbench>_tb
<ip subcores> n
Subcore libraries
sim
Subcore
Simulation files
synth
Subcore
synthesis files
<HDL files> <HDL files>
<your_ip> n
IP variation files
testbench files
Table 3-2: IP Core Generated Files
File Name Description
<my_ip>.qsys The Qsys system or top-level IP variation file. <my_ip> is the name
that you give your IP variation.
3-6 Files Generated for Altera IP Cores
UG-01126
2015.05.04
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