Altera SerialLite III Streaming MegaCore Function - Manual (Page 29)

• For 15.625 Gbps < lane rates < 17.4 Gpbs, the fPLL outputs the
user_clock/user_clock_tx
based on
a fixed ratio, however, the
tx_coreclkin
operates at the same frequency as
tx_clkout
.
Related Information
Sink Clock Generator on page 4-7
Source Application Module
The application module performs the following functions:
• Burst encapsulation—Inserts burst control words into the data stream to define the beginning and the
end of streaming data bursts.
• Idle insertion—Inserts idle control words (in the standard clocking mode) into all lanes of the data
stream interface.
Source Adaptation Module
This module provides adaptation logic between the application module and the Native PHY IP core
(Arria 10 devices) or Interlaken PHY IP (Stratix V and Arria V GZ devices) core. The adaptation module
performs the following functions:
• Rate adaptation—Includes a dual-clock FIFO buffer to cushion the Interlaken PHY IP core's bursty
read requests and to provide a streaming user write interface. The FIFO also transfers streaming data
between the
user_clock
and
tx_coreclkin
clock domains (in standard clocking mode).
• Control signal translation—The state machines maps the control signal semantics on the framing
interface (3) to the semantics of the Native PHY or Interlaken PHY IP core TX interface.
• Non-user idle insertion—Inserts non-user idle control words in the absence of user data to manage the
minimum data rate requirements of the Interlaken protocol. The control words are removed by the
sink adaptation module in the SerialLite III link partner.
Interlaken PHY IP TX Core or Native PHY IP TX Core - Interlaken Mode
For Arria 10 devices, this block is an instance of the Native PHY IP core configured for Interlaken - TX
only operation. For lane rates from 15.625 to 17.4 Gbps, inclusive, the PMA width for Interlaken mode is
64 bits. For lane rates less than 15.625 Gbps, the PMA width is 40 bits.
For Stratix V and Arria V devices, the Interlaken PHY IP TX core is an instance of the Interlaken PHY IP
core configured for TX only operation.The core requires a Transceiver Reconfiguration Controller for
transceiver calibration. The number of channels programmed for configuration in the Transceiver
Reconfiguration Controller depends on the IP core's operation mode. For example,
• if the design is a simplex RX only design, the reconfiguration interfaces is equal to the number of lanes.
• if the design is a simplex TX only design or a duplex design, the reconfiguration interfaces is equal to
the number of lanes x 2.
Related Information
• Arria 10 Transceiver PHY User Guide
For more information about the Arria 10 Native PHY IP core.
(3) The framing interface is to frame every data burst with the Start of Burst, Sync, and End of Burst, and
sequence them to the PHY interface.
UG-01126
2015.05.04
Source Application Module 4-5
SerialLite III Streaming IP Core Functional Description Altera Corporation
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