Altera SerialLite III Streaming MegaCore Function - Manual (Page 47)

Signal Width
Clock Domain
Direction Description
interface_clock 1
core_clock
Output Clock for data transfer across the sink core
interface in the advanced clocking mode.
interface_
clock_reset
1
core_clock
Output The core asserts this signal when the
core_
reset
signal is high and deasserts this signal
when the reset sequence is complete in the
advanced clocking mode.
link_up 1
Standard
clocking: user_
clock
Advanced
clocking: core_
clock
Output The core asserts this signal to indicate that
the core initialization is complete and is
ready to transmit user data.
data 64xN Standard
clocking: user_
clock
Advanced
clocking: core_
clock
Output This vector carries the transmitted streaming
data from the core.
N represents the number of lanes.
sync 8
Standard
clocking: user_
clock
Advanced
clocking: core_
clock
Output The sync vector is an 8 bit bus. The data
value at the start of a burst and at the end of a
burst are captured and transported across the
link.
Note: This vector is not associated with
Interlaken channelization or flow
control schemes.
valid 1
Standard
clocking: user_
clock
Advanced
clocking: core_
clock
Output This single bit signal indicates that the data is
valid.
start_of_burst 1
Standard
clocking: user_
clock
Advanced
clocking: core_
clock
Output When the core is in burst mode operation,
assertion of this signal indicates that the
information on the data vector is the
beginning of a burst.
Because continuous mode is one long burst,
in this mode the signal is asserted only once
at the start of the data.
UG-01126
2015.05.04
Signals 4-23
SerialLite III Streaming IP Core Functional Description Altera Corporation
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