Altera SerialLite III Streaming MegaCore Function - Manual (Page 55)

Signal Width
Clock
Domain
Direction Description
reconfig_to_
xcvr
• Source
core:
140xN
• Sink
core:
70xN
• Duplex
core:
140xN
phy_mgmt_
clk
Input
Dynamic reconfiguration input for the
Interlaken PHY IP. (Stratix V and Arria V
GZ devices only)
N represents the number of lanes.
reconfig_from_
xcvr
• Source
core:
92xN
• Sink
core:
46xN
• Duplex
core:
92xN
phy_mgmt_
clk
Output
Dynamic reconfiguration output for the
Interlaken PHY IP. (Stratix V and Arria V
GZ devices only)
N represents the number of lanes.
tx_serial_data N
—
Output The serial output data from the core.
N represents the number of lanes.
rx_serial_data N
—
Input The serial input data to the core.
N represents the number of lanes.
Note: For Arria 10 devices, the
phy_mgmt
bus interface connects to the reconfiguration interface of the
instantiated Native PHY IP core.
Related Information
Altera Transceiver PHY IP Core User Guide
More information about the Interlaken PHY IP core signals.
UG-01126
2015.05.04
Signals 4-31
SerialLite III Streaming IP Core Functional Description Altera Corporation
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