Altera SerialLite III Streaming MegaCore Function - Manual (Page 22)

Figure 3-6: SerialLite III Streaming Example Testbench (Simplex) for Arria 10 Devices
Device Under Test (Sink)
Testbench
Traffic
Generator
Traffic
Checker
Source
Absorber
Source
Application
Source
Adaptation
Sink
Application
Sink
Adaptation
Sink
Alignment
Source
Clock
Generator
Sink
Clock
Generator
Native
PHY IP
TX -
Interlaken
Mode
Transceiver
TX PLL
Skew
Insertion
Device Under Test (Source)
Test Environment
Native
PHY IP
RX -
Interlaken
Mode
Loopback
Simulating and Verifying the Design
1. Set the environment variables:
• QUARTUS_ROOTDIR to the location of the Quartus II software directory.
• For ModelSim-Altera only: MODELSIM_ALTERA_LIBS to the location of the precompiled
simulation libraries.
2. For simplex mode, set the following environment variables:
• SRC_SIM_LOCATION to the location where the simulation files for the source core are generated.
For instance, if the name of the source core is 'src', then the directory name is /src_sim for Stratix V
and Arria V GZ devices and /src for Arria 10 devices.
• SNK_SIM_LOCATION to the location where the simulation files for sink core are generated. For
instance, if the name of the sink core is 'snk', then the directory name is /snk_sim for Stratix V and
Arria V GZ devices and /snk for Arria 10 devices.
3. For duplex mode, set the following environment variable:
• SIM_LOCATION to the location where the simulation files for the duplex core are generated. For
instance, if the name of the duplex core is 'duplex', then the directory name is /duplex_sim for
Stratix V and Arria V GZ devices and /duplex for Arria 10 devices.
4. Set the parameters in the test_env.v file to override the testbench default value (optional).
5. Run the provided scripts to simulate the testbench in the ModelSim-Altera SE/AE, VCS, VCS MX,
NCSim, or Aldec Riviera simulators. The following table lists the provided scripts.
UG-01126
2015.05.04
Simulating and Verifying the Design 3-13
Getting Started Altera Corporation
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