Altera SerialLite III Streaming MegaCore Function - Manual (Page 61)

The terminal should now display an interactive session for the SerialLite III Streaming IP core design
example.
Related Information
• Development Kits/Cables
• Quartus II Incremental Compilation for Hierarchical and Team-Based Design
More information about the design compilation.
• Nios II Processor
More information about the Nios II processor and its use.
Design Example Operation
Once you download the design and accompanying software into the FPGA, you can test the design
operation through the interactive session. The interactive session provides helpful statistics, as well as
controls for controlling various aspects of the design.
You can control the following operations through the interactive session:
1. Enable source—Enables the traffic generator and start sending out data.
2. Disable source—Disables traffic generation.
3. Reset source—Resets the source core and traffic generator.
4. Reset sink—Resets the sink core and traffic checker.
5. Display error statistics—Displays the error statistics.
6. Toggle burst/continuous mode—Resets the source and sink MACs and toggles the traffic generator to
generate a burst or continuous traffic stream.
7. Toggle CRC error injection for lane 0—Turns CRC error injection off or on for lane 0.
SerialLite III Streaming Link Debugging
The following section describes the link-up sequence that you can use when debugging the SerialLite III
Streaming IP core.
5-6 Design Example Operation
UG-01126
2015.05.04
Altera Corporation SerialLite III Streaming IP Core Design Guidelines
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