Altera SerialLite III Streaming MegaCore Function - Manual (Page 26)

Core Function
Duplex
• Data encapsulation and decapsulation
• Generation and removal of Idle Control Words
• User synchronization and burst marker insertion and deletion
The simplex and duplex cores support the following clocking schemes:
• Standard clocking—This mode is for pure streaming designs in which the core provides input/output
clocks to drive the user logic. Pure streaming operation ensures an exact replica of the output data as it
was presented at the input without any idle cycles at the output (continuous data valid).
• Advanced clocking—This mode allows the core's input interface to be clocked with the user-preferred
clock by trading-off pure streaming operation.
Figure 4-1: SerialLite III Streaming Simplex Core (Standard Clocking)
Application
Module
Adaptation
Module
PHY IP
Transmit
Core (1)
SerialLite III Streaming Source
Source
Reconfiguration
Controller
Interface
Source User
Interface
Application
Module
Adaptation
Module
PHY IP
Receive
Core (1)
SerialLite III Streaming Sink
Sink
Reconfiguration
Controller
Interface
Sink User
Interface
Alignment
Module
N
Lanes
Note:
1. Native PHY IP core for Arria 10 devices and Interlaken PHY IP core for Stratix V and Arria V GZ devices.
Figure 4-2: SerialLite III Streaming Duplex Core (Standard Clocking)
Application
Module
Adaptation
Module
PHY IP
Duplex
Core (1)
SerialLite III Streaming Source
Source
Reconfiguration
Controller
Interface
Source User
Interface
Application
Module
Adaptation
Module
PHY IP
Duplex
Core (1)
SerialLite III Streaming Sink
Sink
Reconfiguration
Controller
Interface
Sink User
Interface
Alignment
Module
N
Lanes
N
Lanes
Application
Module
Adaptation
Module Alignment
Module
Sink User
Interface
Application
Module
Adaptation
Module
Source User
Interface
Note:
1. Native PHY IP core for Arria 10 devices and Interlaken PHY IP core for Stratix V and Arria V GZ devices.
The block diagram for advanced clocking is similar to standard clocking, however, it also includes a PPM
absorption FIFO at the source user interface.
Related Information
Altera Transceiver PHY IP Core User Guide
4-2 IP Core Architecture
UG-01126
2015.05.04
Altera Corporation SerialLite III Streaming IP Core Functional Description
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