Altera SerialLite III Streaming MegaCore Function - Manual (Page 52)

Signal Width
Clock Domain
Direction Description
link_up_rx 1
Standard
clocking:
user_clock
Advanced
clocking:
core_clock
Output The core asserts this signal to indicate that
the core initialization is complete and is
ready to transmit user data.
data_rx 64xN
Standard
clocking:
user_clock
Advanced
clocking:
core_clock
Output
This vector carries the transmitted streaming
data from the core.
N represents the number of lanes.
sync_rx 8
Standard
clocking:
user_clock
Advanced
clocking:
core_clock
Output The sync vector is an 8 bit bus. The data
value at the start of a burst and at the end of a
burst are captured and transported across the
link.
Note: This vector is not associated with
Interlaken channelization or flow
control schemes.
valid_rx 1
Standard
clocking:
user_clock
Advanced
clocking:
core_clock
Output This vector indicates that the data is valid.
start_of_burst_
rx
1
Standard
clocking:
user_clock
Advanced
clocking:
core_clock
Output When the core is in burst mode operation,
asserting this signal indicates that the
information on the data vector is the
beginning of a burst.
Because continuous mode is one long burst,
in this mode the signal is asserted only once
at the start of the data.
end_of_burst_rx 1
Standard
clocking:
user_clock
Advanced
clocking:
core_clock
Output When the core is in burst mode operation,
asserting this signal indicates that the
information on the data vector is the end of a
burst.
You can optionally send an end of burst
signal at the end of continuous mode.
4-28 Signals
UG-01126
2015.05.04
Altera Corporation SerialLite III Streaming IP Core Functional Description
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