Altera SerialLite III Streaming MegaCore Function User Manual

Page 16

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File Name

Description

<system>.sopcinfo

Describes the connections and IP component parameterizations in

your Qsys system. You can parse its contents to get requirements

when you develop software drivers for IP components.
Downstream tools such as the Nios II tool chain use this file.

The .

sopcinfo

file and the

system.h

file generated for the Nios II tool

chain include address map information for each slave relative to each

master that accesses the slave. Different masters may have a different

address map to access a particular slave component.

<my_ip>.cmp

The VHDL Component Declaration (.cmp) file is a text file that

contains local generic and port definitions that you can use in VHDL

design files.

<my_ip>.html

A report that contains connection information, a memory map

showing the address of each slave with respect to each master to

which it is connected, and parameter assignments.

<my_ip>_generation.rpt

IP or Qsys generation log file. A summary of the messages during IP

generation.

<my_ip>.debuginfo

Contains post-generation information. Used to pass System Console

and Bus Analyzer Toolkit information about the Qsys interconnect.

The Bus Analysis Toolkit uses this file to identify debug components

in the Qsys interconnect.

<my_ip>.qip

Contains all the required information about the IP component to

integrate and compile the IP component in the Quartus II software.

<my_ip>.csv

Contains information about the upgrade status of the IP component.

<my_ip>.bsf

A Block Symbol File (.bsf) representation of the IP variation for use

in Quartus II Block Diagram Files (.bdf).

<my_ip>.spd

Required input file for

ip-make-simscript

to generate simulation

scripts for supported simulators. The .spd file contains a list of files

generated for simulation, along with information about memories

that you can initialize.

<my_ip>.ppf

The Pin Planner File (.ppf) stores the port and node assignments for

IP components created for use with the Pin Planner.

<my_ip>_bb.v

You can use the Verilog black-box (_bb.v) file as an empty module

declaration for use as a black box.

<my_ip>.sip

Contains information required for NativeLink simulation of IP

components. You must add the .sip file to your Quartus project.

<my_ip>_inst.v

or

_inst.vhd

HDL example instantiation template. You can copy and paste the

contents of this file into your HDL file to instantiate the IP variation.

UG-01126

2015.05.04

Files Generated for Altera IP Cores

3-7

Getting Started

Altera Corporation

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