Altera SerialLite III Streaming MegaCore Function - Manual (Page 35)

Clock Domain Description
Standard
Clocking
Mode
Advanced
Clocking Mode
Sink
Core
user_clock Sink user interface clock (in standard clocking
mode)
Yes
phy_mgmt_clk Sink Native PHY or Interlaken PHY IP core
reconfiguration interface clock
Yes Yes
xcvr_pll_ref_clk Sink transceiver reference clock
Yes Yes
rx_coreclkin Sink core clock (in standard clocking mode)
Yes
rx_clkout Sink core and user interface clock (in advanced
clocking mode)
Yes
Duplex
Core
user_clock_tx Source user interface clock
Yes Yes
user_clock_rx Sink user interface clock (in standard clocking
mode)
Yes
phy_mgmt_clk Native PHY or Interlaken PHY IP core reconfi‐
guration interface clock
Yes Yes
xcvr_pll_ref_clk Transceiver reference clock
Yes Yes
tx_coreclkin Source core clock (in standard clocking mode) Yes
tx_clkout Source core clock (in advanced clocking mode)
Yes
rx_coreclkin Sink core clock (in standard clocking mode)
Yes
rx_clkout Sink core and user interface clock (in advanced
clocking mode)
Yes
tx_serial_clk
Transmit transceiver clock (Arria 10 only) Yes Yes
Core Clocking
The SerialLite III Streaming IP core comes with standard and advanced clocking modes; select the mode
in the parameter editor.
UG-01126
2015.05.04
Core Clocking 4-11
SerialLite III Streaming IP Core Functional Description Altera Corporation
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