Altera Cyclone III Development Board User Manual
Page 18
2–8
Chapter 2: Board Components
MAX II CPLD
Cyclone III 3C120 Development Board Reference Manual
© March 2009 Altera Corporation
M16
1.8 V
Output
FLASH_OEn
L11
1.8 V
Input
FLASH_RDYBSYn
M15
1.8 V
Output
FLASH_RESETn
L12
1.8 V
Output
FLASH_WEn
J16
1.8 V
Input
FPGA_BYPASS
E3
2.5 V
Input
FPGA_CONF_DONE
D3
2.5 V
Output
FPGA_DATA
C2
2.5 V
Output
FPGA_DCLK
N3
2.5 V
Input
FPGA_JTAG_TCK
N1
2.5 V
Output
FPGA_JTAG_TDI
N2
2.5 V
Input
FPGA_JTAG_TDO
P2
2.5 V
Input
FPGA_JTAG_TMS
E4
2.5 V
Output
FPGA_nCONFIG
C3
2.5 V
Input
FPGA_nSTATUS
N9
1.8 V
Output
FSA[0]
T8
1.8 V
Output
FSA[1]
N10
1.8 V
Output
FSA[10]
R11
1.8 V
Output
FSA[11]
P10
1.8 V
Output
FSA[12]
T12
1.8 V
Output
FSA[13]
M11
1.8 V
Output
FSA[14]
R12
1.8 V
Output
FSA[15]
N11
1.8 V
Output
FSA[16]
T13
1.8 V
Output
FSA[17]
P11
1.8 V
Output
FSA[18]
R13
1.8 V
Output
FSA[19]
T9
1.8 V
Output
FSA[2]
M12
1.8 V
Output
FSA[20]
R14
1.8 V
Output
FSA[21]
N12
1.8 V
Output
FSA[22]
T15
1.8 V
Output
FSA[23]
P12
1.8 V
Output
FSA[24]
R9
1.8 V
Output
FSA[3]
P9
1.8 V
Output
FSA[4]
T10
1.8 V
Output
FSA[5]
K16
1.8 V
Output
FSA[6]
R10
1.8 V
Output
FSA[7]
M10
1.8 V
Output
FSA[8]
T11
1.8 V
Output
FSA[9]
Table 2–5. MAX II Device Pin-Out
(Note 1)
(Part 2 of 8)
MAX II Pin Number
I/O Standard
Signal Direction
Schematic
Signal Name