Altera Cyclone III Development Board - Manual (Page 45)

Chapter 2: Board Components 2–35
General User Interfaces
© March 2009 Altera Corporation Cyclone III 3C120 Development Board Reference Manual
Table 2–40 is an excerpt from the OPTREX data sheet showing pin definitions for both
serial and parallel interfaces. The included display has a parallel interface.
1 Board defaults graphics LCD interface to 80 series CPU mode and parallel interface.
These defaults can be modified by writing to the appropriate register in the MAX II
CPLD using the FSM bus.
Table 2–40. Graphics LCD Pin Definitions
Pin
Number
Parallel I/F
Name Description
1 CS1 Chip select signal L: active
2 RES Reset signal L: reset
3 A0 H: D0 to D7 are display data; L: D0 to D7 are instructions
4 WR 80 family CPU: reset signal L: active
5 RD 80 family CPU: reset signal L: active
6 D0 Display data
7 D1 Display data
8 D2 Display data
9 D3 Display data
10 D4 Display data
11 D5 Display data
12 D6(SCL) Display data (serial data clock signal input)
13 D7(S1) Display data (serial data input)
14 V
D0
Power supply for logic
15 V
SS
Power supply (0 V.GND)
16 V
OUT
DC/DC voltage converter output
17 C3- DC/DC voltage converter negative connection
18 C1+ DC/DC voltage converter positive connection
19 C1- DC/DC voltage converter negative connection
20 C2- DC/DC voltage converter negative connection
21 C2+ DC/DC voltage converter positive connection
22 V
1
Power supply for LCD drive V
1
= 1/9-V
S
23 V
2
Power supply for LCD drive V
2
= 2/9-V
S
24 V
3
Power supply for LCD drive V
3
= 7/9-V
S
25 V
4
Power supply for LCD drive V
4
= 8/9-V
S
26 V
5
Power supply for LCD drive V
5
, V
OUT
27 V
R
Voltage adjustment pin. Applies voltage between V
CC
and V
S
using
a resistive divider
28 C86 Interface mode select signal H:68 series L: 80 series
29 P/S Parallel/serial data select signal H: parallel L: serial
30 N/C Non-connection