Altera Cyclone III Development Board - Manual (Page 77)

© March 2009 Altera Corporation Cyclone III 3C120 Development Board Reference Manual
Additional Information
Revision History
The following table displays the revision history for this reference manual.
Date Version Changes Made
March 2009 1.4 Updated Table 2–10 and Table 2–12 .
December 2008 1.3 Corrected “Schematic Signal Names” in Table 2–47 and Table 2–48 .
August 2008 1.2 ■ Corrected “Schematic Signal Names” in Table 2–5 and added (Note 1) .
■ Updated JTAG settings in Table 2–7 .
■ Updated Table 2–16 .
■ Updated the power supply information of banks 1, 2, 5, and 6 in Figure 2–6 .
■ Updated (Note 1) in Table 2–39 and (Note 1) in Table 2–39 to point to MAX II pin-out
information.
■ Updated “10/100/1000 Ethernet” section.
■ Corrected unit in “Power Measurement” section.
■ Converted document to new frame template and made textual and style changes.
March 2008 1.1 ■ Added schematic information to, revised I/O standard terminology, and added data bit
information to the HSMC Port A and Port B tables.
■ Added schematic information to and revised I/O standard terminology to the DDR 2 interface
I/O table.
■ Added schematic information to and revised I/O standard terminology to the Ethernet PHY
I/O table.
■ Added schematic information to and revised I/O standard terminology to the flash memory
I/O table.
■ Added schematic information to and revised I/O standard terminology to the graphics LCD
table.
■ Added schematic information to and revised I/O standard terminology to the SRAM table.
■ Updated power measurement table.
■ Updated flash memory map table.
■ Added flash memory map definition table.
October 2007 1.0 First publication