Altera Cyclone III Development Board User Manual

Page 60

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2–50

Chapter 2: Board Components

On-Board Memory

Cyclone III 3C120 Development Board Reference Manual

© March 2009 Altera Corporation

U12 pin B3

Data mask 7

SSTL18 Class 1

DDR2_DM7

C20

U13 pin B3

Data mask 8

SSTL18 Class 1

DDR2_DM8

B23

U26 pin G8

Data 0

SSTL18 Class 1

DDR2_DQ0

AG22

U26 pin G2

Data 1

SSTL18 Class 1

DDR2_DQ1

AH21

U26 pin D7

Data 10

SSTL18 Class 1

DDR2_DQ10

AH18

U26 pin D3

Data 11

SSTL18 Class 1

DDR2_DQ11

AH17

U26 pin D1

Data 12

SSTL18 Class 1

DDR2_DQ12

AF15

U26 pin D9

Data 13

SSTL18 Class 1

DDR2_DQ13

AE17

U26 pin B1

Data 14

SSTL18 Class 1

DDR2_DQ14

AF16

U26 pin B9

Data 15

SSTL18 Class 1

DDR2_DQ15

AB16

U25 pin G8

Data 16

SSTL18 Class 1

DDR2_DQ16

AE11

U25 pin G2

Data 17

SSTL18 Class 1

DDR2_DQ17

AG11

U25 pin H7

Data 18

SSTL18 Class 1

DDR2_DQ18

AG10

U25 pin H3

Data 19

SSTL18 Class 1

DDR2_DQ19

AH11

U26 pin H7

Data 2

SSTL18 Class 1

DDR2_DQ2

AH22

U25 pin H1

Data 20

SSTL18 Class 1

DDR2_DQ20

AE9

U25 pin H9

Data 21

SSTL18 Class 1

DDR2_DQ21

AE12

U25 pin F1

Data 22

SSTL18 Class 1

DDR2_DQ22

AF10

U25 pin F9

Data 23

SSTL18 Class 1

DDR2_DQ23

AE13

U25 pin C8

Data 24

SSTL18 Class 1

DDR2_DQ24

AC8

U25 pin C2

Data 25

SSTL18 Class 1

DDR2_DQ25

AH7

U25 pin D7

Data 26

SSTL18 Class 1

DDR2_DQ26

AG8

U25 pin D3

Data 27

SSTL18 Class 1

DDR2_DQ27

AH8

U25 pin D1

Data 28

SSTL18 Class 1

DDR2_DQ28

AG7

U25 pin D9

Data 29

SSTL18 Class 1

DDR2_DQ29

AA10

U26 pin H3

Data 3

SSTL18 Class 1

DDR2_DQ3

AG21

U25 pin B1

Data 30

SSTL18 Class 1

DDR2_DQ30

AF7

U25 pin B9

Data 31

SSTL18 Class 1

DDR2_DQ31

AD10

U11 pin G8

Data 32

SSTL18 Class 1

DDR2_DQ32

A12

U11 pin G2

Data 33

SSTL18 Class 1

DDR2_DQ33

C14

U11 pin H7

Data 34

SSTL18 Class 1

DDR2_DQ34

A11

U11 pin H3

Data 35

SSTL18 Class 1

DDR2_DQ35

C13

U11 pin H1

Data 36

SSTL18 Class 1

DDR2_DQ36

D15

U11 pin H9

Data 37

SSTL18 Class 1

DDR2_DQ37

C12

U11 pin F1

Data 38

SSTL18 Class 1

DDR2_DQ38

E14

U11 pin F9

Data 39

SSTL18 Class 1

DDR2_DQ39

D13

U26 pin H1

Data 4

SSTL18 Class 1

DDR2_DQ4

AD17

U11 pin C8

Data 40

SSTL18 Class 1

DDR2_DQ40

B7

Table 2–51. DDR2 Interface I/O (Part 2 of 5)

Board

Reference

Description

I/O Standard

Schematic

Signal Name

Cyclone III
Device Pin

Number

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