Altera Stratix II GX PCI Express Development Board - Manual (Page 22)

2–12 Reference Manual Altera Corporation
Stratix II GX PCI Express Development Board August 2006
Configuration Schemes and Status LEDs
Configuration
Schemes and
Status LEDs The Stratix II GX device can be configured using two standard
configuration schemes, JTAG and Fast Passive Parallel (FPP). This section
discusses:
■ JTAG configuration
■ FPP configuration
■ Status and channel activity LEDs
JTAG Configuration
JTAG configuration is the simplest way to configure the Stratix II GX
device. The JTAG configuration scheme requires just the USB-Blaster
™
cable and the Quartus ® II Software, Development Kit Edition (DKE),
which are both included with the kit.
For JTAG configuration setup, connect one end of the USB-Blaster cable
to the computer’s USB port and the other end to the 10-pin JTAG header
on the board. To download a design file to the Stratix II GX device, use the
Quartus II Programmer tool.
f
For information on the Quartus II Programmer, refer to Quartus II
Development Software Handbook.
The board’s JTAG chain is connected to the Stratix II GX device, the
MAX II CPLD, and (optionally) the HSMC A and B expansion
connectors. To configure the Stratix II GX device, you need to:
■ Set up a new JTAG chain (including both the MAX II CPLD and the
Stratix II GX device)
■ Set the DIP switch (as noted in “Configuration DIP Switch (S6)” on
page 2–23 ) to remove the HSMC A and B expansion connectors from
the JTAG chain.
Figure 2–7 shows the JTAG chain connections.
156.25 MHz xaui_refclk_cn X3 Stratix II GX pin H8 (REFCLK0_B13n)
xaui_refclk_cp Stratix II GX pin H7 (REFCLK0_B13p)
155.52 MHz SFP_REFCLK_P
SFP_REFCLK_N
X4 P: Stratix II GX pin P7 (RefClk0_B14P)
N: Stratix II GX pin P8 (RefClk0_P14N)
Table 2–4. Stratix II GX PCIe Development Board Clock Distribution (Part 2 of 2)
Frequency Signal Name
Signal
Originates
From
Signal Propagates To