Altera Stratix II GX PCI Express Development Board - Manual (Page 16)

2–6 Reference Manual Altera Corporation
Stratix II GX PCI Express Development Board August 2006
Featured Device
Device Support
The board support’s device migration within all of the following
F1508-packaged Stratix II GX devices:
■ 1.2-V VCCINT
■ 1.2-V to 3.3-V VCCIO
■ 1.2-V to 1.5-V transceiver I/O power
The board’s default device, FF1508 Stratix II GX device, provides the
following:
■ 16 transceiver channels
■ 59 source-synchronous channels
■ 90,960 logic elements (LEs)
■ 8 phase-locked loops (PLLs)
■ 650 user I/O
■ 4,520,448 RAM bits
■ 192 18x18 multipliers
The larger EP2SGX130GF1508 Stratix II GX device provides the
following:
■ 20 transceiver channels
■ 78 source-synchronous channels
■ 132,540 LEs
■ 8 PLLs
■ 798 user I/O
■ 6,747,840 RAM bits
■ 252 18x18 multipliers
I/O & Clocking Resources
This section lists specific I/O and clocking resources available on both the
EP2SGX90FF1508 (default) and the EP2SGX130GF1508 devices.
Figure 2–3 illustrates the available I/O bank resources on both the
EP2SGX90FF1508 and the EP2SGX130GF1508 devices. (The numbers in
parentheses represent the EP2SGX130GF1508 device resources.)