Intel 815 User Manual
Intel, 815 chipset platform
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Table of contents
Document Outline
- Contents
- Figures
- Tables
- Revision History
- Introduction
- General Design Considerations
- Component Quadrant Layouts
- Universal Socket 370 Design
- Universal Socket 370 Definitions
- Processor Design Requirements
- Use of Universal Socket 370 Design with Incompatible GMCH
- Identifying the Processor at the Socket
- Setting the Appropriate Processor VTT Level
- VTT Processor Pin AG1
- Identifying the Processor at the GMCH
- Configuring Non-VTT Processor Pins
- VCMOS Reference
- Processor Signal PWRGOOD
- APIC Clock Voltage Switching Requirements
- GTLREF Topology and Layout
- Power Sequencing on Wake Events
- System Bus Design Guidelines
- System Bus Routing Guidelines
- General Topology and Layout Guidelines
- Electrical Differences for Universal PGA370 Designs
- PGA370 Socket Definition Details
- BSEL[1:0] Implementation Differences
- CLKREF Circuit Implementation
- Undershoot/Overshoot Requirements
- Processor Reset Requirements
- Processor PLL Filter Recommendations
- Voltage Regulation Guidelines
- Decoupling Guidelines for Universal PGA370 Designs
- Thermal Considerations
- Debug Port Changes
- System Memory Design Guidelines
- AGP/Display Cache Design Guidelines
- AGP Interface
- AGP 2.0
- Standard AGP Routing Guidelines
- AGP Down Routing Guidelines
- AGP 2.0 Power Delivery Guidelines
- Additional AGP Design Guidelines
- Motherboard / Add-in Card Interoperability
- AGP / Display Cache Shared Interface
- Designs That Do Not Use The AGP Port
- Integrated Graphics Display Output
- Hub Interface
- I/O Subsystem
- Clocking
- Power Delivery
- System Design Checklist
- Third-Party Vendor Information
- Appendix A: Customer Reference Board (CRB)