Intel 815 - Manual (Page 20)

Introduction
R
20 Intel
®
815 Chipset Platform Design Guide
1.3.2.2 Intel
®
82801AA I/O Controller Hub (ICH)
The I/O Controller Hub provides the I/O subsystem with access to the rest of the system, as
follows:
•
Upstream accelerated hub architecture interface for access to the GMCH
•
PCI 2.2 interface (6 PCI Request/Grant pairs)
•
Bus master IDE controller; supports Ultra ATA/66
•
USB controller
•
I/O APIC
•
SMBus controller
•
FWH interface
•
LPC interface
•
AC’97 2.1 interface
•
Integrated system management controller
•
Alert on LAN*
•
IRQ controller
•
Packaging/Power

241 BGA

3.3V core and 1.8V and 3.3V standby
1.3.2.3 Firmware Hub (FWH)
The hardware features of the firmware hub include:
•
An integrated hardware Random Number Generator (RNG)
•
Register-based locking
•
Hardware-based locking
•
5 GPIs
•
Packaging/Power

40-L TSOP and 32-L PLCC

3.3V core and 3.3V / 12V for fast programming