Intel 815 - Manual (Page 75)

System Memory Design Guidelines
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Intel
®
815 Chipset Platform Design Guide 75
6.4 System Memory Decoupling Guidelines
A minimum of eight 0.1
µ
F low-ESL ceramic capacitors (e.g., 0603 body type, X7R dielectric) are
required and must be as close as possible to the GMCH. They should be placed within at most
70 mils to the edge of the GMCH package edge for VSUS_3.3 decoupling, and they should be
evenly distributed around the system memory interface signal field including the side of the
GMCH where the system memory interface meets the host interface. There are power and GND
balls throughout the system memory ball field of the GMCH that need good local decoupling.
Make sure to use at least 14 mil drilled vias and wide traces from the pads of the capacitor to the
power or ground plane to create a low-inductance path. If possible, multiple vias per capacitor pad
are recommended to further reduce inductance. To add the decoupling capacitors within 70 mils of
the GMCH and/or close to the vias, the trace spacing may be reduced as the traces go around each
capacitor. The narrowing of space between traces should be minimal and for as short a distance as
possible (500 mils maximum).
To further decouple the GMCH and provide a solid current return path for the system memory
interface signals it is recommended that a parallel plate capacitor be added under the GMCH. Add
a topside or bottom side copper flood under center of the GMCH to create a parallel plate
capacitor between VCC3.3 and GND, see following figure. The dashed lines indicate power plane
splits on layer 2 or layer 3 depending on stack-up. The filled region in the middle of the GMCH
indicates a ground plate (on layer 1 if the power plane is on layer 2 or on layer 4 if the power layer
is on layer 3).